1. Field of the Invention
The present invention relates to a decoder circuit and decoding method thereof, and more particularly to a decoder circuit and decoding method thereof which decoder circuit is included in a semiconductor integrated circuit (IC).
2. Description of the Related Art
Nowadays, in a semiconductor IC, device dimensions are being minimized and the volume of their memory is being increased year by year. Accordingly, in order to make the semiconductor IC have a higher speed, it is needed to realize minimization (hereinafter "minimization" refers to minimization of dimensions) of memory cells (referred to as "MC" hereinafter) thereof and, minimization and high speed of circuits disposed around the MC.
FIG. 1 shows an example for illustrating the circuits disposed around the MC. In this diagram, based on decoder-circuit selecting signals supplied by an address decoder 10 and clock signals supplied by a clock buffer 20, decoder circuits 30-1 to 30-n are selected so as to generate respective word line signals WL1 to WLn.
The address decoder 10 is supplied with memory address signals A0 to Am from an outside portion (not shown), and generates the decoder-circuit selecting signals based on these memory address signals A0 to Am. For example, the address decoder 10 generates a decoder-circuit selecting signal for selecting the decoder circuit 30-1 in a case in which a memory address signal indicates a memory address controlled by the word line WL1 outputted from the decoder circuit 30-1.
Next, the decoder circuits 30-1 to 30-n are described with reference to FIG. 2 showing an example of these decoder circuits. As seen from this diagram, each of the decoder circuits 30-1 to 30-n includes a NAND circuit 31 and NOT circuits 32 to 34. The NAND circuit 31 is supplied with two decoder-circuit selecting signals and a clock signal, and, for example, when the three supplied signals are all high, a high-level word line signal is outputted from the NOT circuit 34.
However, in these conventional decoder circuits, there is a problem that, as the volume of the memory of the MC is increased, a load increases over lines through which the decoder-circuit selecting signals for selecting the decoder circuits pass. Furthermore, in order to realize a higher speed of the semiconductor IC, it is needed to minimize the MC, and minimize and make high speed the circuits disposed around the MC, of which circuits the decoder circuits are particularly desired to be minimized.